The electronic industry is currently dealing with increasingly larger application specific integrated circuit (ASIC) products. A digital simulation of an entire ASIC design imposes a significant burden in terms of central processing unit (CPU) time and hardware resources (i.e., workstation memory). Even if a small portion of the ASIC circuit is simulated, an electronic design automation (EDA) simulator consumes significant hardware resources and CPU time loading the gate-level netlist and back-annotating the design with timing data. A typical example situation is the validation of a test program that addresses a specific module of the ASIC, such as a built-in self test (BIST) pattern for a block of the ASIC design or a memory-BIST pattern for a specific set of memories.